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A review of critical device parameters helps to explain differences in the behaviors of DMOS and LDMOS transistors.
TRANSISTOR users have been besieged in recent years by a variety of different RF device structures, notably those based on metal-oxidesemiconductor (MOS) processes. For high-power amplification at verv hi-high fiFe uencv (VHF), ultra-high frequency (UHF), and higher frequencies, the MOS field-effect transistor (MOSFET) has come to challenge silicon-bipolar transistors as the device of choice. Several different MOSFET devices are available, and understanding the differences in their structures can help during the selection process. This first installment of a two-part article examines some of the structural differences between two leading types of MOSFET devices. Research on MOSFET devices has predominantly focused on very-largescale-integration (VLSI) technology, driven mainly by computer integrated-circuit (IC) market pressures. VLSI devices are structurally similar to RF power MOSFETs, but with much-smaller dimensions. In contrast to VLSIs, RF power MOSFETs feature larger channel lengths, greater junction depths, and much-thicker gate oxides in order to handle the higher power levels required for RF applications.
There are two major RF MOSFET structures currently in use-doublediffused-metal-oxide-semiconductor (DMOS) and laterally-diffused-MOS (LDMOS) structures. The unique behaviors of these devices are dependent on geometries and semiconductor processes. These devices are fabricated in two common configurations-p-type MOS (PMOS) and ntype MOS (NMOS) devices. The following discussion will focus on the NMOS configuration.
Figures 1 and 2 depict the physical structures of DMOS and LDMOS devices, respectively. It is apparent that LDMOS is predominantly a lateral surface-effect device. The DMOS geometry incorporates large vertical and lateral structures, with significant lateral- and vertical-current components.
These MOSFETs are three-terminal devices (assuming that the substrate is shorted to the source), with the terminals commonly identified as the source, gate, and drain. The voltage on the gate controls the current flowing from the drain to the source. The most common circuit layout for these devices is the common-source (CS) configuration, which is comparable (in some respects) to the bipolar transistor's common-emitter (CE) configuration.
In the CS configuration, any frequency-dependent source-to-ground connection will introduce negative feedback. Other configurations are used with MOSFETs, but...