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Ensuring the security of a design is an increasingly important issue to system developers, particularly as more designers are beginning to make use of the substantial advantages of field programmable gate arrays (FPGAs).
Using FPGAs reduces the development time, and many studies have shown the necessity of hitting the market window at the right time to make the most of the opportunity. However, this ease of use has its downside in its vulnerability to reverse engineering.
Historically, design security has been the concern of the military and high revenue products such as gambling and gaming equipment. But with more FPGA designs and more market areas where encryption and data security is vital, such as wireless networks, design security is becoming increasingly important.
The major problem with FPGAs based on an SRAM memory cell architecture is that the configuration data has to be fed into the FPGA when the system boots up. Simply placing an oscilloscope between the boot PROM and the FPGA (Fig. 1) gives the configuration bit stream, which can then be copied and used in a competitive system.
A solution is to have a battery back up mode where the bitstream is loaded into the FPGA on the manufacturing line and kept live using a backup battery. This adds the cost of the battery sub-system, and means the equipment has to be returned to the factory for re-programming if the battery runs down or fails.
Design protection...