Content area
Full Text
Silicon technology continues to outpace design methodologies. A million-gate design is a reality, but implementing it is another matter altogether. The Semiconductor Industry Association (SIA) predicts there will be more than 10-million transistors on a single integrated circuit (IC) by next year. According to SIA, in the next two years, more than half of all system on chip designs will be based on previously implemented designs.
The latest generation of deep submicron (DSM) processes enables SOC design, though it has produced a productivity gap. Designing one large system-level IG takes more effort than designing individual components that made up the original chip-set or board.
At the same time, product life cycles are shorter with each new generation, demanding shorter design cycles. Semiconductor processes have a shorter life spans with each new generation - as short as 18 months for 0.25-It processes - forcing design teams to implement a form of process independence into their environments.
Finally, DSM effects are making the final mask design stage more critical and time consuming because of increased parasitic effects that influence functionality and timing. The problem is reaching critical proportions.
The answer is found in developing a different design methodology. Reusing hard intellectual property (IP) - designs represented as mask layouts - by migrating it to more competitive processes offers endless possibilities. Hard IP reuse is an attractive solution, when formerly redesign was accomplished using synthesis. Hard IP reuse is reliable and requires less effort for the creation of the final mask layout.
But first, some definitions. Hard IP has been verified in silicon and is available as a physical layout in GDS2 format. Functionality and timing are known and are based on a particular process technology. All IP verified in silicon can be made available in a hard form.
Soft IP is available as a netlist or a hardware description language (HDL) description. As pre-verified and synthesized software blocks, it offers flexibility, but it needs to be functionally verified. It is easily modified, but requires re-placement and rerouting at the layout level, the equivalent of a complete redesign and a new silicon verification cycle.
...