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The cost of testing complex system-on-chip designs will soon surpass the cost of manufacturing them. Clearly this is an unstable situation. It is simply too hard to keep up with Moore's Law. While the automatic test equipment industry keeps an impressive and steady annual productivity improvement of 15 to 25 percent, this is not good enough to keep Moore's Law at bay.
Costs associated with systemon-chip (SoC) testing are pretty simple. There is a setup for each chip test thatincludes a tester program and a test jig. Then there is the tester itself. For complex, high-speed SoC devices, testers cost between $2,000 and $9,000 per pin. Commonly, these chips have many hundreds of pins, so testers cost many millions of dollars. The current path of test equipment evolution cannot be continued. Testing 100-million-- transistor designs through 200 access pins with an 800-MHz clock creates a burden too heavy for ATE providers to bear.
With new process technologies becoming available every 18 months, new testers are required in the same time frame for the high-end devices. These facts make tester time very expensive and, in fact, they dwarf the one-- time costs associatedwith the development of the tester program and fabrication of the test jig.
There are only a few strategies for reducing the cost of test:
* Test less. This is not viable because the further bad devices get into the system assembly process, the more expensive the failure becomes.
* Test more efficiently-apply methods that reduce the time it takes to apply a set of tests.
* Test differently-use alternative test types and strategies that cost less.
* Lower the cost of testers. This is everybody's favorite answer, and there is actually some hope it might...