Fabrication and Circuit Modeling of NMOS Inverter Based on Quantum Dot Gate Field-Effect Transistors

Journal of ELECTRONIC MATERIALS, Vol. 41, No. 8, 2012

DOI: 10.1007/s11664-012-2116-4

2012 TMS

Fabrication and Circuit Modeling of NMOS Inverter Based on Quantum Dot Gate Field-Effect Transistors

SUPRIYA KARMAKAR,1,2,3,4 JOHN A. CHANDY,1 MUKESH GOGNA,1

and FAQUIR C. JAIN1

1.Department of Electrical and Computer Engineering, University of Connecticut, 371, Faireld Way, U-2157, Storrs, CT 06269-2157, USA. 2.Present address: Intel Corporation, Hillsboro, OR 97124, USA. 3.e-mail: [email protected]. 4.e-mail: [email protected]

This paper presents the fabrication of a negative-channel metaloxidesemiconductor (NMOS) inverter based on quantum dot gate eld-effect transistors (QDG-FETs). A QDG-FET produces one intermediate state in its transfer characteristic. NMOS inverters based on a QDG-FET produce three states in their transfer characteristic. The generation of the third state in the inverter characteristic makes this a promising circuit element for multivalued logic implementation. A circuit simulation result based on the Berkley simulation (BSIM) circuit model of the QDG-FET is also presented in this paper, predicting the fabricated device characteristic.

Key words: Quantum dot gate FET, three-state FET, NMOS inverter, three-state NMOS inverter

INTRODUCTION

Metaloxidesemiconductor eld-effect transistors (MOSFETs) produce only two states in their transfer characteristics. According to Moores law, electronic industries are always thinking about miniaturization of electronic devices. Starting from small-scale integration (SSI) technology, silicon industry has already achieved ultralarge-scale integration (ULSI) technology and is now in nano-meter (nm)-scale integration. The degree of integration can be increased by decreasing the size of the individual devices as well as increasing their bit-handling capacity. Multivalued logic circuits can be implemented based on quantum dot gate eld-effect transistors. Until now, multivalued logic has not reached maturity because of the lack of proper semiconductor devices.

Researchers are trying to implement multivalued logic using conventional eld-effect transistors (FETs) with different architectures.16 However, the main problem is the complication in the circuit design as well as delay, rise time, fall time, and power dissipation. New devices are required for

multivalued logic implementation. Different promising semiconductor devices such as resonant tunneling diodes (RTDs),79 resonant tunneling transistors (RTTs),1013 modulation-doped eld-effect transistors (MODFETs),1416 and high-electron-mobility transistors (HEMTs),1719 which produce negative differential resistance (NDR), have been proposed for multivalued logic implementation. Since the basic operation principle of these devices is band-to-band tunneling of charge carriers, the main problem with these devices is the high valley current because...