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ABSTRACT
Today in the era of modern technology micro electronics play a very vital role in every aspects of life of an individual, increasing use for micro electronics equipments increases the demand for manufacturing its components and its availability, reducing its manufacturing time, resulting in increasing the failure rate of the finished product. In order to overcome this problem the Technocrats develop a method called Verification, a process which is a part of manufacturing microelectronics products. So approximately 30% of the effort spent on the average project is consumed by design and 70% in verification. For this reason, methods which improve the efficiency and accuracy of hardware design and verification are immensely valuable. The current VLSI design scenario is characterised by high performance, complex functionality and short time-tomarket. A reuse based methodology for S°C design has become essential in order to meet these challenges. The work embodied in this paper presents the design of APB 3 Protocol and the Verification of slave APB 3 Protocol. Coverage analysis is a vital part of the verification process; it gives idea that to what degree the source code of the DUT has been tested. The Functional coverage analysis increases the verification efficiency enabling the verification engineer to isolate the areas of un-tested function. The design and verification IP is built by developing verification components using Verilog and System Verilog respectfully with relevant tools such as Rivera, which provides the suitable building blocks to design the test environment.
KEYWORDS: AMBA (Advanced Microcontroller Bus Architecture), APB(Advanced peripheral Bus), Functional coverage analysis, RTL (Register Transfer Level) design, System Verilog, SOC (System on chip), DUT (Design Under Test), Design intellectual property (DIP), Verification intellectual property (VIP).
I. INTRODUCTION
Intellectual Property (IP) Cores are of first line of choice in the development of Systems-on-chip (SOC). Typically, a S°C is an interconnection of different pre-verified IP blocks which communicate using complex protocols. Approaches adopted to facilitate plug and- play style IP reuse include the development of a few standard on-chip bus architectures such as CoreConnect[11] from IBM, AMBA[9] from ARM among others, and the work of the VSI Alliance[8] and the OCP-IP[10] consortium. Designers are usually provided with voluminous specifications of the protocols used by the IP blocks and the underlying bus architecture....