Case Studies of Batch Processing Experiments

Headnote

Abstract

Experimentation in the semiconductor industry requires clever design and clever analysis. In this paper, we look at two experiments performed at International SEMATECH. The first is a strip plot design of 3 factors over 3 process steps. The second is a split plot design at a cleaning operation. The importance of using the correct error terms in testing the model will be discussed.

Keywords

strip plot, split plot, multiple experimental units, multiple error terms, randomization restriction

1. Introduction

Wafer processing in the semiconductor industry is complex. Wafers can be run through a tool one at a time or batched together for processing. When designing experiments for wafer processing, the experimenter must not only consider the experimental design (e.g., factorial structure), but also the execution of the treatment combinations. Most Design of Experiments (DOE) classes teach one execution style, the completely randomized design (CRD). The CRD fails when randomization of experimental units to treatment combinations must be restricted. Randomization restriction often occurs in the semiconductor industry either because experiments cover more than one process step or they involve factors that are hard to vary. In either case, running a CRD would be too expensive in terms of time, materials, and costs associated with the number of runs a tool must make.

Two designs that are useful in the semiconductor industry are the strip plot and split plot. Each design requires more wafers than a traditional CRD, but allows batching of wafers and is still able to test all effects. The commonality to these designs is the concept of multiple experimental units (the entity which receives the treatment) and hence multiple error terms in the model. Failure to identify the correct experimental units can lead to incorrect analysis and misleading conclusions.

This paper discusses two case studies of experiments performed at International Sematech (ISMT). The first is a strip plot design that was performed as part of a large study trying to identify the cause of via chain resistance failures. This experiment studied yield over an ash and two etch operations. The strip plot design is necessary since wafers are batched together at each operation. The second case study is a split plot design run for process optimization at a wafer clean step. In addition...