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A 17/24 GHz dual-band CMOS low-noise amplifier (LNA) for ISM-band application is presented. The proposed LNA employs a positive feedback transmission-line-based LC-ladder network to obtain dual-band operation and reduce power consumption. For low cost, the LNA has been fabricated using a 0.18 μm mixed-signal CMOS process. The implemented LNA shows gains of 9.2 and 12 dB, and noise figures (NF) of 5.7 and 6.4 dB at 18 and 24.5 GHz, respectively. The proposed LNA exhibits 8 mW power consumption from a 0.8 V supply and the active chip area, including pad, is about 720 × 460 μm^sup 2^.
Introduction: As wireless applications expand, requirements for a radio that can support multi-bands and multi-standards are continuously increasing. In a single-chip radio, a low noise amplifier (LNA) plays an important role in the noise performance or sensitivity of the total receiver chain. Although up to now a number of broadband and dualband LNAs have been reported with good performance in CMOS technology, most previous work has focused on a low frequency range, below 10 GHz. In general a dual-band LNA can be achieved by combining two LNAs in parallel for each narrow band [1]. However, this approach demands twice the power dissipation, a large chip area and therefore a significant increase in cost. Recently the low power and compact-sized dual-band LNA using a switching inductor, capacitor and concurrent method also has been reported [2-4]. In this Letter a low power concurrent dual-band LNA is proposed which is suitable for 17.1-17.3 GHz and 24-24.25 GHz industrial, scientific and medical (ISM) band application.
Circuit design: The schematic diagram of the proposed LNA is shown in Fig. 1. Since a cascode amplifier, which is widely used for high gain, significantly degrades noise and gain at high frequencies, three-stage common...