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Abstract
Advances in networking and data processing speeds have led to the need for high-speed cryptosystems. The speed of a cryptosystem is function of its complexity and the technology used to implement it. This work investigates the techniques of designing fast modulo multipliers since modulo-multiplication is a basic essential operation in public-key cryptography. Two types of modulo multipliers have been designed and modeled using VHDL and MatLab. While the first multiplier is based on asynchronous adder design, the other multiplier is based on four-to-two compressor design. In addition, a Built In Self Test (BIST) methodology has been developed for the Compressor based multiplier design. The two multiplier designs have been evaluated and compared based on their area-delay cost.
