Content area
Abstract
The reliabililty of electrostatic discharge (ESD) protection devices and circuits are investigated. By understanding the characteristics and limitations of each protection device, the ESD robustness of the entire protection circuit can then be determined.
The effects of high electric field transients on thin, 55 A to 200 A, gate oxides were studied to determine the new requirements for future ESD protection circuits. For many applications, transistor threshold shifts, not oxide breakdowns, will be the limiting factor in determining maximum transient voltages. Thinner oxides are more susceptible than thicker oxides. The effects of dynamic stressing on oxide lifetime and the use of oxides grown on textured single-crystal silicon (TSC oxides) were also examined. Oxides have longer time-to-breakdowns for dynamic stressing when compared to DC stressing. TSC oxides have improved oxide reliability making them an interesting dielectric for certain non-volatile memory applications.
An integral part of most ESD protection circuits is the lateral bipolar breakdown/snapback action of MOSFETs. A three-dimensional substrate spreading resistance model is presented. With this model, the maximum voltage before snapback can be calculated and the channel width effect on MOSFET breakdown can be explained. The high current snapback characteristics of MOSFETs with different channel lengths and widths, gate oxide thicknesses, and substrate dopings were examined. The results suggest that decreasing the transistor channel length, which decreases the snapback voltage, can improve the ESD protection in terms of failures due to both thermal damage and oxide breakdown.
The oxide breakdown and MOSFET breakdown/snapback results are incorporated into an ESD failure simulator. This simulator also calculates the temperature rise within the protection circuit to determine if failures due to silicon melting or aluminum contact melting occur. The circuit simulator SPICE is used to determine internal voltage and current transients. These internal transients are verified with a specially fabricated test circuit. Good agreement between the simulated failure results and published data was observed.
