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12.8 Gigabyte/second Bandwidth ilo Bus Solution Builds on PCI Bus Concepts to Deliver High Performance for Embedded Systems
The next generation of 1GHz+ high performance embedded processors are causing a paradigm shift in how I/O buses are deployed in networking and communications systems. This next generation of embedded processors, which are based on high speed, low power 32- and 64-bit RISC-like architectures, provide specialized functionality with integrated DRAM controllers, Gigabit Ethernet, PCI, and integrated Low Voltage Differential Signaling buses (LVDS). With this class of processor placed at the center of networking and communications systems, architects can achieve a new level of performance and integration and can do so with less risk, shorter design cycles, and a reduced price per channel.
These highly integrated processors and tightly coupled LVDS 1/0 and DRAM memory buses provide the enhancements needed to perform tasks from simple network routing to realtime packet classification and deep packet processing. However, communications protocols for connecting systems and networks are advancing at a pace where total integration of all possible I/O buses on the processor becomes impractical if not impossible. Hence the need for standardized Control, Data, and Look-aside interfaces to facilitate a high-speed mezzanine bus to Application Specific Network ICs such as Data-encryption, Deep-packet processors, Packet classifiers as well as bridges to current and future I/O standards such as PCI-X, SPI-4, 10-Gigabit Ethernet, etc.
Legacy I/O bus architectures are still widely used in embedded systems because they are low cost and easily implemented using established software and hardware standards. But, these single ended, half duplex buses have limited per pin performance. Today's RISC processors operating at 1 GHz+ and I/O standards exceeding 10Gbps need a faster alternative to these low bandwidth buses with a growth option to support vastly higher data rates.
The HyperTransport technology I/O bus, developed by the HyperTransport Consortium, delivers the vastly higher data rates needed for high performance applications in networking, communications, and other embedded applications-in a flexible, extensible, and easily implemented mezzanine bus structure. The HyperTransport I/O bus standard was designed specifically as an "in the box" interconnect with state-of-the-art 1.25 volt sub 0.13u processes in mind. The HyperTransport technology solution provides a broad selection of bus widths and speeds that can fit the power,...