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Abstract
Successive approximation register analog to digital converter (SAR ADC), which mostly consists of digital components, is becoming more and more popular in recent years as it is power efficient and friendly to process scaling. However, the two-step structure, which is widely used for medium or high-resolution SAR ADCs, usually contains a closed-loop residue amplifier that is not friendly to technology scaling. As transistors continue to scale, the intrinsic gain of transistors and supply voltage drop, which post challenges on the design of high gain amplifiers for the closed-loop residue amplifier. To ease the amplifier design in advanced processes, a linearized open-loop amplifier with expansive loading compensation is explored in this project as a residue amplifier. The incomplete settling technique is also employed in the design to lower the power consumption of the amplifier. Schematic simulation in GF65nm shows that the ADC achieves 65dB SNDR, 88dB SFDR while consuming 5mW at the sampling rate of 400MS/s.
