Analysis of Random Variation in Subthreshold FGMOSFET

Abstract

The analysis of random variation in the performance of Floating Gate Metal Oxide Semiconductor Field Effect Transistor (FGMOSFET) which is an often cited semiconductor based electronic device, operated in the subthreshold region defined in terms of its drain current ([subscript]ID[/subscript] ), has been proposed in this research. [subscript]ID[/subscript] is of interest because it is directly measurable and can be the basis for determining the others. All related manufacturing process induced device level random variations, their statistical correlations, and low voltage/low power operating condition have been taken into account. The analysis result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy. By using such result, the strategies for minimizing variation in [subscript]ID[/subscript] can be found and the analysis of variation in the circuit level parameter of any subthreshold FGMOSFET based circuit can be performed. So, the result of this research has been found to be beneficial to the variability aware design of subthreshold FGMOSFET based circuit.

[ProQuest: [...] denotes non US-ASCII text; see PDF]

Academic Editor:Jinlong Liu

Department of Computer Engineering, Siam University, 235 Petchakasem Road, Bangkok 10163, Thailand

Received 21 April 2016; Accepted 26 June 2016

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1. Introduction

The FGMOSFET in subthreshold region has been found to be an extensively utilized semiconductor based electronic device for low voltage/low power circuits [1-16]. The concept of variability aware design has been applied to such low voltage/low power circuits for handling the effects of the manufacturing process induced device level random variations [6, 10-16]. The examples of these variations are the variation in channel width (W) and channel length (L) and so forth. These device level variations affect the circuit level performances of FGMOSFET such as _ID , transconductance (_gm ), and drain to source resistance (_rds ). Similar to the ordinary Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the subthreshold FGMOSFET is more susceptible to these variations than that in the above-threshold region and _ID has been found to be the key circuit level performance as it is directly measurable and can be the basis for determining the others according to their relationships.

According to the importance of _ID , various analyses of random variation in _ID of the ordinary MOSFET caused by manufacturing process induced device level random variations have been performed in the analytical manner where the subthreshold region operated MOSFET has also been concerned [17-23]. For FGMOSFET, on the other hand, the previous studies have been mostly focused on variations in the circuit level performances of certain FGMOSFET based circuits where subthreshold FGMOSFET based circuits have also been considered [6, 10-12, 15, 23-29]. Unfortunately, the analysis results of these previous researches are applicable only to their dedicated circuits. Moreover, the variability analysis of a single subthreshold FGMOSFET, which is more versatile as it is applicable to any subthreshold FGMOSFET based circuits, has never been performed in any previous work.

Hence, the analysis of random variation in _ID (Δ_ID ) of subthreshold FGMOSFET caused by manufacturing process induced device level random variations has been proposed in this research. All related device level random variations, their statistical correlations, and low voltage/low power operating condition have been taken into account. The obtained analysis result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy. By using the obtained result, the strategies for minimizing Δ_ID can be found and the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit can be done. So, the result of this research has been found to be beneficial to the variability aware design of subthreshold FGMOSFET based circuit which is an interesting low voltage/low power semiconductor application. In the next section, the overview of FGMOSFET will be addressed followed by the proposed analysis in Section 3. The verification of the analysis result and discussions will be, respectively, given in Sections 4 and 5. Finally, the conclusion will be drawn in Section 6.

2. The Overview of FGMOSFET

FGMOSFET is a special type of MOSFET with an additional gate, namely, floating gate isolated within the oxide. A cross-sectional view of an N-type FGMOSFET with N inputs where N>1 can be shown as in Figure 1 where the symbol and equivalent circuit are shown in Figure 2. Such equivalent circuit is composed of a MOSFET, N input capacitances (_C1 ,_C2 ,_C3 ,...,_CN ), overlap capacitance between floating gate and drain (_Cfd ), overlap capacitance between floating gate and source (_Cfs ), and parasitic capacitance between floating gate and substrate (_Cfb ).

Figure 1: A cross-sectional view of N-type, N inputs FGMOSFET.

[figure omitted; refer to PDF]

Figure 2: The symbol (a) and equivalent circuit model (b) of an N-type, N inputs FGMOSFET.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

Let {i}={1,2,3,...,N} and let any ith input capacitance be denoted by _Ci ; the floating gate voltage, _VFG , can be given by [figure omitted; refer to PDF] where _Vi is the input voltage at any ith input gate, _VD is the drain voltage, _VS is the source voltage, and _VB is the bulk voltage. Moreover, Q^ stands for the charge stored on the floating gate. Finally, _CT denotes the total capacitance of the floating gate which can be defined as [figure omitted; refer to PDF]

Let _ki , _kfd , _kfs , and _kfb denote the coupling factor of any ith input gate, drain, source, and bulk and be defined as _ki =_Ci /_CT , _kfd =_Cfd /_CT , _kfs =_Cfs /_CT , and _kfb = _Cfb /_CT , respectively; _VFG can be alternatively given as in (3). From either (1) or (3), it can be seen that _VFG depends on _Vi , _VD , _VS , and _VB : [figure omitted; refer to PDF] where Q denotes charge stored on the floating gate per _CT and is equal to Q^/_CT .

3. The Proposed Analysis

By using _VFG as given by (3), _ID of the subthreshold region operated FGMOSFET can be given without assuming that 1>>exp[...][-_VDS /_VT ] for covering the low voltage/low power operating condition which may have very low _VDS that invalidates this assumption, as [figure omitted; refer to PDF] where _I0 , n, _VDS , and _VT stand for subthreshold specific current which depends on various physical parameters, for example, gate oxide capacitance (_Cox ) and threshold voltage (_Vth ), subthreshold parameter, drain to source voltage, and thermal voltage, respectively.

Since the variations in W (ΔW), L (ΔL), Q (ΔQ), n (Δn), _I0 (Δ_I0 ), _kfd (Δ_kfd ), _kfs (Δ_kfs ), _kfb (Δ_kfb ), and _ki (Δ_ki ), which are related to manufacturing process of the FGMOSFET, contribute Δ_ID of our interest, Δ_ID can be given in terms of its contributors as [figure omitted; refer to PDF] where variations in the physical parameters of _I0 , for example, those in _Cox (Δ_Cox ) and _Vth (Δ_Vth ), have been taken into account by Δ_I0 . By using (4), derivatives in (5) can be given by [figure omitted; refer to PDF]

From (5)-(6), it can be seen that Δ_ID is very mathematically cumbersome. So, it is worthy to look for the alternative manners of analysis, for example, the per-unit based analysis which performs the analysis in terms of the per-unit value of Δ_ID (Δ_ID /_ID ). By using (4)-(6), Δ_ID /_ID can be given as follows: [figure omitted; refer to PDF] where ΔW/W, ΔL/L, ΔQ/Q, Δn/n, Δ_I0 /_I0 , Δ_kfd /_kfd , Δ_kfs /_kfs , Δ_kfb /_kfb , and Δ_ki /_ki are the per-unit values of ΔW, ΔL, ΔQ, Δn, Δ_I0 , Δ_kfd , Δ_kfs , Δ_kfb , and Δ_ki , respectively.

Since it has been found that Δ_ID /_ID is much more compact than Δ_ID , the per-unit based analysis is preferable and has been chosen for this research. It has also been found that Δ_I0 and ΔW contribute Δ_ID in the similar directions which are opposite to that of ΔL. Finally, the directions of contributions to Δ_ID of Δn, Δ_kfd , Δ_kfs , Δ_kfb , and Δ_ki depend on _Vi , _VS , _VD , and _VB whereas that of ΔQ is solely dependent on the polarity of Q. As Δ_ID /_ID is a random variable similar to its contributors, that is, ΔW, ΔL, ΔQ, Δn, Δ_I0 , Δ_kfd , Δ_kfs , Δ_kfb , and Δ_ki , it is convenient to analyze its statistical behavior by using its standard deviation as its mean is equal to zero similar to those of the contributors. By taking the statistical correlations of the contributors into account, the standard deviation of Δ_ID /_ID (^{σΔ_ID /_ID} ) has been found to be given by [figure omitted; refer to PDF] where ^σΔX/X2 denotes the variance of ΔX/X and {ΔX/X}={ΔW/W,ΔL/L,ΔQ/Q,Δn/n,Δ_I0 /_I0 ,Δ_kfd /_kfd ,Δ_kfs /_kfs ,Δ_kfb /_kfb ,Δ_ki /_ki }. Moreover, ^ρΔX,ΔY denotes the correlation coefficient of ΔX and ΔY which displays the degree of their statistical correlation; for example, _ρΔW,ΔL denotes the correlation coefficient of ΔW and ΔL and displays the degree of their statistical correlation. It can be seen from (8) that the 1st up to the 9th terms of ^{σΔ_ID /_ID} have been solely contributed by each of ^σΔX/X2 's where the others have been contributed by the statistical correlations based terms. Moreover, by keeping in mind that ΔW, ΔL, ΔQ, Δn, Δ_I0 Δ_kfd , Δ_kfs , Δ_kfb , and Δk are zero mean random variables, ^ρΔX,ΔY can be obtained by using (9) where E(·) stands for the expectation operator: [figure omitted; refer to PDF]

4. Verification of the Analysis Result

The proposed analysis result has been verified at the nanometer level based on the 65 nm level CMOS process technology, two-input FGMOSFET of both N-type and P-type, and SPICE BSIM4 [30] with all necessary SPICE parameters provided by PTM. Since two-input FGMOSFET has been assumed, we let N=2; that is, {_Ci }={_C1 ,_C2 } and {_ki }=(_k1 ,_k2 ). It should be noted that both _k1 and _k2 can be arbitrary constants as our device is not in the triode region which is the only region of FGMOSFET that the coupling factors are functions of _VD [31]. So, we let _k1 =_k2 =0.5 in order to balance the influence of both FGMOSFET inputs. We also let W=120 nm and L=80 nm and also assume that _Ci >>_Cfd ,_Cfs ,_Cfb and Q^ is extremely small as has been done in many previous works on subthreshold FGMOSFET, for example, [1-3, 6-8, 11, 15]. For making the influences of all device level variations be unbiased, all of such variations have been assumed to be statistically equivalent by letting them be normally distributed with zero means and 1% standard deviations. As a result, ΔXΔY such as ΔWΔL employs a normal product distribution [32] as the products of the manufacturing process induced device level random variations, for example, ΔWΔL, Δ_I0 ΔQ, and ΔnΔL, are the product of two normally distributed random variables. Moreover, all _ρΔx,Δy 's have been assumed to be given by 0.5 which is a reasonable estimation [33]. So, each device level variation must be expressed in terms of a weighted sum of its correlated and uncorrelated components which are both normally distributed [33] and have equal weights given by 0.5.

In order to perform the verification, the formulated ^{σΔ_ID /_ID} has been compared to its SPICE BSIM4 based reference (_{(^{σΔID /ID} )SPICE} ) obtained by using the Monte-Carlo SPICE simulation with 1000 runs. The SPICE BSIM4 based modelling of FGMOSFET with two inputs can be done by using the two-input version of the equivalent circuit of FGMOSFET in Figure 2 where the core MOSFET has been modelled by using the SPICE BSIM4 and the simulation methodology proposed in [34] has been adopted for solving the convergence problem of the simulator.

As the resulting verification, ^{σΔ_ID /_ID} and _{(^{σΔID /ID} )SPICE} have been comparatively plotted against the magnitude of the voltage of the 1st and 2nd input of FGMOSFET denoted by (_V1 ) and (_V2 ), respectively. The minimum values of both (_V1 ) and (_V2 ) are 0 volts and the maximum values have been chosen so that the both N-type and P-type FGMOSFETs operate in the subthreshold region. The comparative plots of ^{σΔ_ID /_ID} and _{(^{σΔID /ID} )SPICE} against (_V1 ) (where (_V2 )=0) of N-type and P-type subthreshold FGMOSFET can be shown in Figure 3 where the similar plots against (_V2 ) (where (_V1 )=0) are shown in Figure 4.

Figure 3: N-type and P-type subthreshold FGMOSFET based comparative plots against (_V1 ) where (_V2 )=0.

[figure omitted; refer to PDF]

Figure 4: N-type and P-type subthreshold FGMOSFET based comparative plots against (_V2 ) where (_V1 )=0.

[figure omitted; refer to PDF]

From Figures 3 and 4 where ^{σΔ_ID /_ID} and _{(^{σΔID /ID} )SPICE} have been, respectively, shown in blue lines and red dots for N-type subthreshold FGMOSFET (green lines and black dots for P-type device), highly strong agreements between ^{σΔ_ID /_ID} and _{(^{σΔID /ID} )SPICE} can be observed. Moreover, the average errors of ^{σΔ_ID /_ID} from _{(^{σΔID /ID} )SPICE} determined by using the data sets of Figure 3 have been found to be 1.6245% and 1.8904% for N-type and P-type subthreshold FGMOSFET based comparison. On the other hand, such errors determined by using the data sets of Figure 4 have been found to be 1.8244% and 1.9518% for the N-type and P-type device based comparison, respectively. This means that the analysis result is very accurate for both N-type and P-type subthreshold FGMOSFET. If desired, ^{σΔ_ID /_ID} can fit _{(^{σΔID /ID} )SPICE} obtained by using the data from more advanced technology node, for example, 45 nm, 32 nm, and 28 nm. For doing so, the optimum parameters of subthreshold MOSFET's _ID such as _I0 , n, W, and L, extracted from the measured _ID of the advanced technology node under consideration by using the optimization algorithm [35], must be adopted.

From Figures 3 and 4, it can be seen that ^{σΔ_ID /_ID} of the subthreshold FGMOSFET of both N-type and P-type grow larger when either (_V1 ) or (_V2 ) are lowered. This implies that the subthreshold FGMOSFET under very low voltage/low power operating condition is subjected to very large Δ_ID . It can also be seen that both ^{σΔ_ID /_ID} 's with respect to (_V1 ) and (_V2 ) of the P-type subthreshold FGMOSFET are lower than those of the N-type device. This means that the P-type device is more robust to the manufacturing process induced device level random variations than its N-type counterpart and has been found to be more preferable. Finally, even though the aforementioned average errors of the P-type device are larger than those of the N-type counterpart, it does not mean that our analysis result is more suitable to the less robust device. This is because the differences in these average errors which are very small as they are less than 0.3% are caused by the differences between the extraction errors of the subthreshold MOSFET's drain current analytical model parameters from the 65 nm level CMOS technology based drain current data of the N-type and P-type MOSFET.

5. Discussions

Since the subthreshold FGMOSFET under very low voltage/low power operating condition is subjected to very large Δ_ID as stated above, omitting such condition in the designing of those circuits with crucial variability related issues has been found to be a simple strategy to avoid large Δ_ID . However, this strategy is not recommended according to the necessity of such condition for obtaining the low voltage/low power circuit. As a result, the operating condition regardless of strategies for minimizing Δ_ID must be determined. Fortunately, these strategies can be obtained by using our formulated Δ_ID /_ID given by (7). From this equation, it can be seen that [figure omitted; refer to PDF]

Obviously, (10)-(18), respectively, determine the contributions of Δ_I0 , ΔW, ΔL, ΔQ, Δn, Δ_kfd , Δ_kfs , Δ_kfb , and Δ_ki to Δ_ID . So, minimizing them yields the minimization of Δ_ID . It can be seen that (∂Δ_ID /_ID )/(∂Δ_I0 /_I0 ), (∂Δ_ID /_ID )/(∂ΔW/W), and (∂Δ_ID /_ID )/(∂ΔL/L) are constant, so, they cannot be minimized by any means. On the other hand, (∂Δ_ID /_ID )/(∂ΔQ/Q) is proportional to Q, (∂Δ_ID /_ID )/(∂Δn/n), (∂Δ_ID /_ID )/(∂Δ_kfd /_kfd ), (∂Δ_ID /_ID )/(∂Δ_kfs /_kfs ), (∂Δ_ID /_ID )/(∂Δ_kfb /_kfb ), and (∂Δ_ID /_ID )/(∂Δ_ki /_ki ) are inversely proportional to n, and (∂Δ_ID /_ID )/(∂Δn/n), (∂Δ_ID /_ID )/(∂Δ_kfd /_kfd ), (∂Δ_ID /_ID )/(∂Δ_kfs /_kfs ), and (∂Δ_ID /_ID )/(∂Δ_kfb /_kfb ) are proportional to _kfd , _kfs , and _kfb , that is, proportional to _Cfd , _Cfs , and _Cfb . Thus, it can be seen that Δ_ID can be minimized by minimizing Q, _Cfd , _Cfs , and _Cfb and maximizing n. In order to do so, Q can be minimized by several means such as using UV shining [13] and using a dummy stacked contact [36]. On the other hand, the effects of _Cfd , _Cfs , and _Cfb can be minimized by ensuring that _Cfd ,_Cfs ,_Cfb <<_Ci . Moreover, n can be maximized by minimizing the oxide capacitance per-unit area between the floating gate and the bulk.

Apart from yielding the above strategies, our Δ_ID /_ID is also applicable to the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit in which the formulated ^{σΔ_ID /_ID} given by (8) has been found to be beneficial as well. For performing such analysis, we let the circuit level performance of the subthreshold FGMOSFET based circuit of our interest be P; thus, the random variation in P (ΔP) can be given by [figure omitted; refer to PDF] where M, _IDk , and Δ_IDk /_IDk denote number of FGMOSFETs within the circuit which contribute P, _ID , and Δ_ID /_ID of any kth FGMOSFET which can be determined by using (7), respectively. It can be seen from (19) that ΔP can be determined after every Δ_IDk /_IDk has been found.

According to the definition of Δ_IDk /_IDk above, it is a zero mean random variable and so does ΔP. As a result, it is convenient to analyze the statistical behavior of ΔP by using its standard deviation, that is, ^σΔP . By taking the statistical correlations between each random variation in _IDk into account, ^σΔP can be given by (20), where _{ρΔIDk ,ΔIDl} denotes the correlation coefficient of Δ_IDk and Δ_IDl which are the random variations in _IDk and _IDl , that is, _ID of any lth FGMOSFET where l≠k, respectively. Since ^{σΔ_IDk /_IDk} and ^{σΔ_IDl /_IDl} are, respectively, ^{σΔ_ID /_ID} of kth and lth FGMOSFET, they can be determined by using (8). After finding all ^{σΔ_IDk /_IDk} 's and ^{σΔ_IDl /_IDl} 's, ^σΔP can be obtained: [figure omitted; refer to PDF]

As a practical example, let P be the output current (_Iout ) of the subthreshold FGMOSFET based OTA [11] whose core circuit has been depicted in Figure 5 where ^V+ (^V- ) and _VDD denote the voltage at the positive (negative) input of the OTA and the supply voltage, respectively. For this OTA, _M1 and _M2 which have two inputs serve as an input differential pair and the averaging circuit has been included for improving the linearity. According to [11], _Iout can be given in terms of _ID of _M1 and _M2 , that is, _ID1 and _ID2 as [figure omitted; refer to PDF]

Figure 5: The core circuit of the subthreshold FGMOSFET based OTA proposed in [11].

[figure omitted; refer to PDF]

Since the bodies of these FGMOSFETS are grounded and their sources are tied together as shown in Figure 5, we have _VB1 =_VB2 =0 and _VS1 =_VS2 . Thus, we can let both _VS1 and _VS2 be given by _VS . As a result, _ID1 and _ID2 can be, respectively, given by [figure omitted; refer to PDF] where _k11 (_k21 ), _k12 (_k22 ), _kfd1 (_kfd2 ), and _kfs1 (_kfs2 ) stand for _k1 , _k2 , _kfd , and _kfs of _M1 (_M2 ). These coupling factors can be given by [figure omitted; refer to PDF] where _C11 (_C21 ), _C12 (_C22 ), _Cfd1 (_Cfd2 ), _Cfs1 (_Cfs2 ), and _Cfb1 (_Cfb2 ) stand for _C1 , _C2 , _Cfd , _Cfs , and _Cfb of _M1 (_M2 ), respectively.

So, the random variation in _Iout (Δ_Iout ) can be given by using (19) with M=2 as [figure omitted; refer to PDF] where both Δ_ID1 /_ID1 and Δ_ID2 /_ID2 can be determined by using (7) as they are Δ_ID /_ID of _M1 and _M2 . For determining Δ_ID1 /_ID1 , we let N=2, _V1 =^V+ , _V2 =_VDD , _k1 =_k11 , _k2 =_k12 , _kfd = _kfd1 , _kfs =_kfs1 , and _VB1 =0 in (7). For determining Δ_ID2 /_ID2 on the other hand, we let N=2, _V1 =^V- , _V2 =_VDD , _k1 =_k21 , _k2 =_k22 , _kfd =_kfd2 , _kfs =_kfs2 , and _VB2 =0.

Moreover, the standard deviation of Δ_Iout (^σΔ_Iout ) can be obtained by using (20) with M=2 as follows: [figure omitted; refer to PDF] where ^{σΔ_ID1 /_ID1} and ^{σΔ_ID2 /_ID2} can be determined by using (8) as they are ^{σΔ_ID /_ID} of _M1 and _M2 . Similar to determining Δ_ID1 /_ID1 and Δ_ID2 /_ID2 , we let N=2, _V1 =^V+ , _V2 =_VDD , _k1 =_k11 , _k2 =_k12 , _kfd =_kfd1 , _kfs =_kfs1 , and _VB1 = 0 for determining ^{σΔ_ID1 /_ID1} and let N=2, _V1 =^V- , _V2 =_VDD , _k1 =_k21 , _k2 =_k22 , _kfd =_kfd2 , _kfs =_kfs2 , and _VB2 =0 for determining ^{σΔ_ID2 /_ID2} . Finally, we can plot ^σΔ_Iout against ^{σΔ_ID1 /_ID1} and ^{σΔ_ID2 /_ID2} as shown in Figure 6 where ^σΔ_Iout has been expressed in a per-unit basis with respect to the nominal _Iout and the magnitude of _{ρΔID1 ,ΔID2} has been assumed to be 0.5 which implies a reasonable medium degree of correlation between Δ_ID1 and Δ_ID2 . From Figure 6, it can be seen that ^σΔ_Iout is increased with respect to ^{σΔ_ID1 /_ID1} and ^{σΔ_ID2 /_ID2} . It can also be seen that even small amounts ^{σΔ_ID1 /_ID1} and ^{σΔ_ID2 /_ID2} can induce considerably large ^σΔ_Iout . As an example, ^{σΔ_ID1 /_ID1} =0.09 and ^{σΔ_ID2 /_ID2} =0.08, that is, Δ_ID1 and Δ_ID2 of 9% and 8% of the nominal I_D1 and I_D2 , respectively, yield ^σΔ_Iout =0.26 which is equivalent to Δ_Iout as large as 26% of the nominal _Iout . So, it can be seen that the adverse effect of Δ_ID to the performance of subthreshold FGMOSFET based circuits is significant.

Figure 6: The 3D plot ^σΔ_Iout of the subthreshold FGMOSFET based OTA versus ^{σΔ_ID1 /_ID1} and ^{σΔ_ID2 /_ID2} .

[figure omitted; refer to PDF]

6. Conclusion

In this research, the analysis of Δ_ID of subthreshold FGMOSFET, which is an often cited semiconductor based electronic device, has been performed. All related device level random variations, that is, ΔW, ΔL, ΔQ, Δn, and Δ_I0 which cover variations in the physical parameters of _I0 , for example, Δ_Cox and Δ_Vth , Δ_ki , Δ_kfd , Δ_kfs , and Δ_kfb and their statistical correlations, have been taken into account. Moreover, the low voltage/low power operating condition has also been concerned. The obtained result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy where the average error of each verification scenario has been, respectively, found to be 1.6245% (1.8904%) and 1.8244% (1.9518%) for N-type (P-type) subthreshold FGMOSFET.

Based on the proposed analysis result, it has been found that the subthreshold FGMOSFET under low voltage/low power operating condition is subjected to large Δ_ID and the P-type subthreshold FGMOSFET has been found to be a more preferable device as it is more robust to the manufacturing process induced device level random variations than its N-type counterpart. It has also been found that Δ_ID can be minimized by minimizing Q, _Cfd , _Cfs , and _Cfb , maximizing n, and avoiding the extremely low voltage/low power operating condition. The design technics for obtaining minimum Q, _Cfd , _Cfs , and _Cfb and maximum n have been suggested. Moreover, the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit can be done based on the proposed result as illustrated above in which the subthreshold FGMOSFET based OTA has been focused on. So, the result of this research has been found to be beneficial to the variability aware analysis and design of subthreshold FGMOSFET based circuit which is an interesting semiconductor application.

Acknowledgments

The author would like to acknowledge Mahidol University, Thailand, for the online database service.

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